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CPU Simulation
4 days ago 80f3c31 20250525.sharded-cache pull_requestCompare
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Comparefeat: sharded in-memory stores + #[concurrent_cached] default
#264
20250525.sharded-cache
4 days ago
CPU Simulation
16 total
LruCache hit
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)555.3 ns
LruTtlCache hit (O(1))
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)1.2 µs
RwLock UnboundCache write lock read
benches/cache_benches.rs::benches::bench_lock_synchronization::Lock Contention & Synchronization643.3 ns
ExpiringCache hit (O(1))
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)402.8 ns
TtlCache insert (no eviction)
benches/cache_benches.rs::benches::bench_cache_misses_and_inserts::Cache Misses & Inserts810.6 ns
RwLock UnboundCache unsync read
benches/cache_benches.rs::benches::bench_lock_synchronization::Lock Contention & Synchronization675.3 ns
UnboundCache insert
benches/cache_benches.rs::benches::bench_cache_misses_and_inserts::Cache Misses & Inserts381.1 ns
TtlCache hit (O(1))
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)966.1 ns
ExpiringLruCache hit (O(1))
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)555.3 ns
TtlSortedCache hit
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)921.1 ns
LruTtlCache eviction overhead
benches/cache_benches.rs::benches::bench_eviction_overhead::Eviction & Capacity Limits1.6 µs
LruCache eviction overhead
benches/cache_benches.rs::benches::bench_eviction_overhead::Eviction & Capacity Limits1.3 µs
UnboundCache hit
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)581.1 ns
ExpiringCache insert
benches/cache_benches.rs::benches::bench_cache_misses_and_inserts::Cache Misses & Inserts437.5 ns
LruCache insert (no eviction)
benches/cache_benches.rs::benches::bench_cache_misses_and_inserts::Cache Misses & Inserts795 ns
LruTtlCache insert (no eviction)
benches/cache_benches.rs::benches::bench_cache_misses_and_inserts::Cache Misses & Inserts1.2 µs