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CPU Simulation
3 days ago 70cb5ac master pushCompare
Suggested base runs:
16 total
ExpiringCache hit (O(1))
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)431.9 ns
LruTtlCache insert (no eviction)
benches/cache_benches.rs::benches::bench_cache_misses_and_inserts::Cache Misses & Inserts1.3 µs
ExpiringLruCache hit (O(1))
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)526.1 ns
TtlCache insert (no eviction)
benches/cache_benches.rs::benches::bench_cache_misses_and_inserts::Cache Misses & Inserts839.7 ns
LruCache hit
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)526.1 ns
UnboundCache insert
benches/cache_benches.rs::benches::bench_cache_misses_and_inserts::Cache Misses & Inserts410.3 ns
LruTtlCache hit (O(1))
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)1.1 µs
LruCache eviction overhead
benches/cache_benches.rs::benches::bench_eviction_overhead::Eviction & Capacity Limits1.2 µs
TtlCache hit (O(1))
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)936.9 ns
LruTtlCache eviction overhead
benches/cache_benches.rs::benches::bench_eviction_overhead::Eviction & Capacity Limits1.7 µs
RwLock UnboundCache write lock read
benches/cache_benches.rs::benches::bench_lock_synchronization::Lock Contention & Synchronization370.3 ns
RwLock UnboundCache unsync read
benches/cache_benches.rs::benches::bench_lock_synchronization::Lock Contention & Synchronization372.8 ns
TtlSortedCache hit
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)897.2 ns
UnboundCache hit
benches/cache_benches.rs::benches::bench_cache_hits::Cache Hits (O(1) Reads)276.4 ns
LruCache insert (no eviction)
benches/cache_benches.rs::benches::bench_cache_misses_and_inserts::Cache Misses & Inserts765.8 ns
ExpiringCache insert
benches/cache_benches.rs::benches::bench_cache_misses_and_inserts::Cache Misses & Inserts437.5 ns