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CPU Simulation
3 months ago 6dc6863 master workflow_dispatchCompare
Suggested base runs:
13 total
amortized[InternedInput]
benches/compare.rs::benches::inputs::Mutating Inputs2.2 µs
new[SupertypeInput]
benches/compare.rs::benches::inputs::Mutating Inputs15.7 µs
new[Input]
benches/compare.rs::benches::inputs::Mutating Inputs9.9 µs
mutating[20]
benches/compare.rs::benches::mutating_inputs::Mutating Inputs14.4 µs
mutating[30]
benches/compare.rs::benches::mutating_inputs::Mutating Inputs14.3 µs
converge_diverge_nested
benches/dataflow.rs::benches::nested110.8 µs
mutating[10]
benches/compare.rs::benches::mutating_inputs::Mutating Inputs13.7 µs
accumulator
benches/accumulator.rs::benches::accumulator3.3 ms
amortized[SupertypeInput]
benches/compare.rs::benches::inputs::Mutating Inputs2.7 µs
converge_diverge
benches/dataflow.rs::benches::dataflow143.7 µs
amortized[Input]
benches/compare.rs::benches::inputs::Mutating Inputs2.2 µs
new[InternedInput]
benches/compare.rs::benches::inputs::Mutating Inputs4.5 µs
many_tracked_structs
benches/incremental.rs::benches::many_tracked_structs8.9 µs